1. Field of Invention
This invention relates to a clock recovery circuit, and in particular, to a multi-channel clock recovery circuit where multiple channels use a common voltage controlled oscillator (VCO).
2. Discussion of Related Art
As data traffic increases, for example, through use of the Internet, there has developed a need for high-speed, high-bandwidth communications equipment. Consequently, there is also a demand for integrated circuits for use in that equipment. Because of the speed and density of such integrated circuits, it is important that the circuits are designed to operate at low power. One type of integrated circuit is a clock recovery circuit used in serial data transmission.
In digital communications systems, it is often desirable to transmit serially digital data between remote sites. In serial communication, a single optical fiber or wire (for example, coaxial or twisted-pair) carries a serial stream of data bits, often at data rates of 1.25 Ghz or greater. This method also requires that the serial data be accompanied by a synchronous clock so that a digital receiver is able to properly register the incoming serial data. In other words, the synchronous clock informs the receiver of when each serial data bit has arrived.
However, it is often difficult or impractical to transmit a synchronous clock along with the serial data. Fortunately, the clock data needed by a remote receiver to register the serial bit stream is often encoded within the serial data. The circuitry by which the clock data is recovered from the data stream is called a clock recovery circuit. The clock recovery circuit extracts information contained within the serial data bit stream to generate a clock that is synchronous with the serial data bit stream. For example, the clock recovery circuit can inspect the serial data transitions to determine the frequency and phase of the incoming serial bit stream.
A typical clock recovery circuit is shown in FIG. 38. The clock recovery circuit is arranged in a phase locked loop configuration and includes a phase detector 200 and a voltage controlled oscillator (VCO) 201. The VCO 201 generates even and odd half-speed output clocks CLKEVEN and CLKODD having a relative phase difference of 180xc2x0. The term xe2x80x9chalf-speed clockxe2x80x9d refers to a clock having a frequency of half the data rate of the received data. As configured, the even input data of DIN is registered with the rising edges of CLKEVEN and the odd input data is registered with the rising edge of CLKODD. In this manner, two clocks operating at half-speed can be used to synchronize corresponding input data. This arrangement is valuable because slower reference clocks require lower power and are easier to generate and control. Further, slower clocks have more favorable waveforms and are less susceptible to noise.
VCO 201 also generates a fall-speed feedback reference clock at approximately the same frequency as the input data rate of DIN. The frequency and phases of CLKEVEN, CLKODD, and the feedback reference clock are controlled by the input voltage Vin of the VCO 201. If the voltage supplied to the input of the VCO 201 increases, the frequency and phase of the output clocks CLKEVEN, CLKODD, and the feedback reference clock increases, and if the voltage to the input of the VCO decreases, the frequency and phase of the output clocks CLKEVEN, CLKODD, and the feedback reference clock decreases.
The phase detector 200 analyzes the input data DIN over one bit period and determines whether the feedback reference clock leads or lags the input data DIN. If the feedback reference clock lags the phase of the input data DIN, the phase detector 200 increases the voltage at the input of VCO 201 thereby causing VCO 201 to increase the phase/frequency of the feedback reference clock, CLKEVEN, and CLKODD. If the feedback reference clock leads the phase of the input data DIN, the phase detector 200 decreases the voltage at the VCO 201 input thereby causing the VCO 201 to decrease the phase/frequency of the feedback reference clock, CLKEVEN, and CLKODD. Thus, the feedback reference clock and even/odd clocks (CLKEVEN/CLKODD) tend to synchronize with the phase and frequency of the input data DIN in a closed loop fashion.
FIG. 39 shows a typical waveform of input serial data DIN at high frequency. The input data xe2x80x9ceyexe2x80x9d pattern is the superposition of the input data trace as a function of time over one bit period. In functional language, EYE=Input Data (t+nT), where t is less than or equal to T. Because the serial input data DIN is being received at such a high frequency (e.g., 1.25 GHz), and over various non-linear medium, the serial data is likely to be significantly distorted in amplitude and phase. As can be seen, sampling the input data near the transition of the input data eye could easily lead to an error due to the distorted waveform of high speed data stream DIN. In other words, the value of the input data DIN, measured near the transition points (high-to-low or low-to-high), could mistakenly be recorded as a xe2x80x9c1xe2x80x9d when it is properly a xe2x80x9c0xe2x80x9d or a xe2x80x9c0xe2x80x9d when it is properly a xe2x80x9c1xe2x80x9d. As shown, a sampling point where there is the highest probability that the data will be sampled correctly is half-way between the transition points of the input data DIN. This point is referred to as the middle of the xe2x80x9ceyexe2x80x9d of the input data. Therefore, it is important to synchronize CLKEVEN and CLKODD so that their registering clock edges occur as close as possible to the middle of the xe2x80x9ceyexe2x80x9d of the even and odd data, respectively.
A practical data communication system often contains multiple channels of serial data streams. This necessitates duplication of the clock recovery circuit for each channel. However, the power consumption becomes prohibitively high when implementing multiple VCOs on a semiconductor die. To reduce power consumption, it is therefore desirable to employ a common VCO for all of the clock recovery circuits. However, when multiple channels of serial input data are received, the input data in each channel may vary slightly in frequency and significantly in phase with respect to the input data in one or more of the other channels. Therefore, the same VCO can not be used for each PLL in conventional multi-channel clock recovery circuits. Accordingly, there is a need for a multi-channel clock recovery circuit that is capable of using of a common VCO to drive multiple clock recovery circuits for multiple channels.
An object of the invention is to overcome the aforementioned problems and limitations of conventional clock recovery circuits. Another object is to provide a multi-channel clock recovery circuit that uses a single VCO. Another object is to provide a multi-channel clock recovery circuit that operates at low power. Another object is to provide an efficient inverting phase multiplexor that selects clock phases from a clock generator without causing glitches in the clock. Another object is to provide an efficient interpolating phase multiplexor that selects clock phases without causing glitches in the clock. Another object is to provide a multi-channel clock recovery circuit having a two stage filter. Another object is to provide a multi-channel clock recovery circuit using a single VCO with a plurality of output clocks on a phase bus, where the clock recovery circuit has a layout that minimizes the length of the phase bus.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect of the invention there is provided a multiple (or single) channel digital clock recovery circuit for generating and using quadrature clocks operating at half the speed of the incoming data rate of each channel, wherein a pair of the half speed quadrature clocks have an inverse phase relationship and are capable of registering input data of a channel at the center of the input data eye. The other pair of the half speed quadrature clocks have an inverse phase relationship and are 90 and 270 degrees away from the first pair, respectively, and are in the middle of the transition region of the input data eye respectively.
The quadrature phases of the half speed clocks span two input data eyes and in a given cycle there could be as many as two transitions of the input data. The position where each of the data transitions occur relative to the four phases of the quadrature clocks are analyzed using a digital phase detector and implementing the following algorithm: the sum of transitions between quadrature phases 270 degrees and 0 degrees and 90 degrees and 180 degrees should be same as the sum of transitions between quadrature phases 0 degrees and 90 degrees and 180 degrees and 270 degrees. This condition provides feedback to a phase multiplexor circuit, which selects the four quadrature phases with the above relationship from a plurality of phases of half-speed clocks, generated by VCO of an analog PLL, to satisfy above described criteria. The decision of changing selected phases, based upon above criteria is filtered through a digitally programmable filter for desired performance for the above digital clock recovery circuit for each channel.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provided further explanation of the invention as claimed.